邮箱：cnj@ahpu.edu.cn
主要学习与工作经历：
2009.03-2013.03 同济大学计算机系统结构专业获工学博士学位；
2013.11-2016.11 天津大学计算机科学与技术专业获博士后证书；
2014.01-2014.12 中国科学院计算技术研究所计算机体系结构国家重点实验室学习；
2005.04-至今安徽工程大学工作(博士，博士后，教授，CCF容错计算专委，CCF集成电路设计专委，CCF高级会员)。
联系邮箱：chennaijin@ict.ac.cn； naijinchen6@163.com。
研究方向：
可重构计算系统编译计算，计算机视觉，情感计算。
承担的主要科研项目：
近年来参与或主持国家863项目、国家重点研发计划项目、国家自然科学基金重点项目、安徽省自然科学基金面上项目、 安徽省教育厅自然科学基金重点项目等16项。
代表性科研成果：
以第一作者发表学术论文30余篇，授权软件著作权和发明专利10项，代表性的论文列举如下：
[01]Naijin Chen*, et al.Compute-Intensive Loop Scheduling and Optimized Mapping on CGRA [J].IEEE Transactions on Computers
(review)
[02]Naijin Chen*, Fei Cheng,Chenghao Han,Jianhui Jiang,Xiaoqing Wen.Loop Subgraph-Level Greedy Mapping Algorithm for Grid Coarse-Grained Reconfigurable Array [J].Tsinghua Science and Technology, 2023,2(28): 330-343.(中科院1区，SCI,EI)
[03]Naijin Chen*, Zhen Wang, Ruixiang He, Jianhui Jiang, Fei Cheng, Chenghao Han.Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture [J].Tsinghua Science and Technology, 2021, 26(5): 724-735.(中科院1区，SCI,EI)
[04]Naijin Chen*, Feng Zhiyong, Jiang Jianhui, He Ruixiang, Wang Zhen. Pipeline Mapping Performance Evaluation for Row Parallel Reconfigurable Cell Array [J].Journal of Tongji University(Natural Science), 2017, 45(8): 1218-1226.(EI)
[05]Naijin Chen*，Feng Zhiyong.Interconnect Delay Performance Evaluation for Non-Crossing Leveland Row Operands Parallel RCA[J].Journal of Tianjin University(Science and Technology),2017,50(4):429-436. (EI)
[06]Naijin Chen*,Jiang Jianhui.Mapping Algorithm of Coarse Grained Reconfigurable Cell Array for Multibranch Tree Data Flow Graph[J].Journal of Computer-Aided Design & Computer Graphics. 2016,28(7):756-766.(EI)
[07]Naijin Chen*,Jiang Jianhui. Considering Communication-Cost and Hardware-Fragment Utilization Cluster Partitioning Algorithm[J].Journal of Computer-Aided Design & Computer Graphics. 2015,27(4):754-763.(EI)
[08]Naijin Chen*,Jiang Jianhui.A Multi-Objective Optimization Mapping Algorithm for Coarse Grained Reconfigurable Architectures[J].Chinese Journal of Electronics. 2015, 43 (11):2151-2160.(EI)
[09]Naijin Chen*, Feng Zhiyong, Jiang Jianhui.Bypass node non-redundant adding algorithm for crossing-level data transmission in two-dimension reconfigurable cell array[J].Journal on Communications.2015,36(4):2015132:1-17. (EI)
[10]Naijin Chen*, Jiang Jianhui. Hardware-task partitioning algorithm merged area estimation with multi-objective optimization[J].Journal on Communications, 2013,34(2):40-55. (EI)
[11]Naijin Chen*,Jiang Jianhui,Chen Xin,Zhou Zhou,Xu Yin.An Improved Level Partitioning Algorithm Considering Minimum Execution Delay and Resource Restraints[J].Chinese Journal of Electronics. 2012,40(5):1055-1066.(EI)
[12]Naijin Chen*, Jianghui Jiang. Mapping algorithm for coarse-grained reconfigurable multimedia architectures.IEEE International Parallel&& istributed Processing Symposium (IPDPS), Shanghai, IEEE CS Press, Shanghai, China, 2012, pp. 281-286.(EI, CCF-B)
[13]Wang Zhen, Jiang Jianhui, Naijin Chen*, Lu Guangming, Zhang Ying. Effects of Thee Factors Under BTI on the Soft Error Rate of Integrated Circuits. [J].Journal of Computer Research and Development, 2018, 55 (5): 1108-1116. (EI)
学术专著
[1] 陈乃金. 可重构计算系统模型资源划分映射方法研究[M].西安：西安交通大学出版社，2023
所获奖励：
[1] 2006年获安徽工程大学校级青年教师教学基本功竞赛二等奖；
[2] 2009年获安徽工程大学第12届“教学优秀奖”三等奖；
[3] 《平面型RTD制作过程中的两个关键工艺》获安徽省第六届自然科学学术论文三等奖。